1. Field of the Invention
Embodiments of the present invention generally relate to a processor based hardware emulation system and, more particularly, to a heterogeneous processor based hardware emulation system.
2. Description of the Related Art
Hardware emulators are programmable devices used to verify hardware designs. A common method of hardware design verification is to use processor-based hardware emulators to emulate the design prior to physically manufacturing the integrated circuit(s) of the hardware. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
An exemplary hardware emulator is described in commonly assigned U.S. Pat. No. 6,618,698 titled “Clustered Processors In An Emulation Engine”, which is hereby incorporated by reference in its entirety. Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware.
The complexity and number of logic gates present on an integrated circuit has increased significantly in the past several years. Hardware emulators need to improve in efficiency to keep pace with the increased complexity of integrated circuits. The speed with which a hardware emulator can emulate an integrated circuit is one of the most important benchmarks of the emulator's efficiency, and also one of the emulator's most important selling factors in the emulator market.
Conventional hardware emulators are comprised of identical processors. The processors are generally arranged into groups of processors known as clusters. In a conventional hardware emulator, each processor performs an identical set of functions, i.e., retrieving data from a memory, evaluating the data, and writing the processed result back to the memory. Processors address the memory via an instruction word. The instruction word is stored in a special instruction memory and contains a read address for the data to be evaluated and a Boolean function table that instructs the processor on how to evaluate the data. The processor then stores the produced result back to the same memory location as indicated by the instruction address.
The amount of memory required by a conventional hardware emulator is directly dependent on the number of processors present in the hardware emulator. Specifically, the hardware emulator must contain a memory that is at least equal to the number of processors multiplied by the depth of the instruction memory. The instruction word must contain several address fields to enable the processor to address any location within the memory. Also, during each instruction execution cycle, each processor must perform numerous energy-consuming read and write accesses to the memory.
Thus, there is a need in the art for a hardware emulator that contains more processors than a conventional hardware emulator but does not require substantially more memory.